The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

May. 10, 2016
Applicant:

Suss Microtec Lithography Gmbh, Garching, DE;

Inventors:

Hale Johnson, Jericho, VT (US);

Gregory George, Colchester, VT (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/677 (2006.01); H01L 21/687 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67742 (2013.01); H01L 21/6719 (2013.01); H01L 21/67092 (2013.01); H01L 21/67748 (2013.01); H01L 21/6838 (2013.01); H01L 21/68707 (2013.01); H01L 21/68721 (2013.01); H01L 21/68742 (2013.01); H01L 24/75 (2013.01); H01L 24/83 (2013.01);
Abstract

An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.


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