The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2017
Filed:
Sep. 12, 2012
Donovan Popps, Austin, TX (US);
Amjad Qureshi, San Jose, CA (US);
Donovan Popps, Austin, TX (US);
Amjad Qureshi, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A system-on-chip (SOC) () is interfaced with a memory () formed by a plurality of stacked memory integrated circuit dies (-). The SOC () includes a memory controller () that has a built-in self-test (BIST) system () for performing the testing and repair of memory (). BIST system () includes a microcode processor () that communicates externally to the SOC () through a Joint Test Action Group interface () and is coupled to a BIST state machine () for executing a memory specific test sequence to detect faults in memory (). The microcode processor () further communicates with a repair state machine () to execute memory specific repair procedures responsive to memory faults being detected.