The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2017
Filed:
Jan. 27, 2015
Cadence Design Systems, Inc., San Jose, CA (US);
Dongzi Liu, Fremont, CA (US);
Deng Pan, Newark, CA (US);
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
A system, method and/or computer program for optimizing a circuit design. In some embodiments, a target block with an external boundary and external boundary pins is identified in an integrated circuit design. An area outside the target block is converted into a first macro, wherein the first macro has a physical library and a timing library and wherein the physical library has an internal boundary that corresponds to the external boundary of the target block and wherein the physical library has internal boundary pins that correspond to the external boundary pins of the target block. The target block is represented as a single block netlist and the block netlist is optimized with respect to the first macro. The steps may be repeated with respect to a master and clone(s) on the same integrated circuit enabling a single block netlist to be optimized for multiple instances of the same design IP.