The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Nov. 13, 2009
Applicant:

Anthony J. Suto, Sterling, MA (US);

Inventor:

Anthony J. Suto, Sterling, MA (US);

Assignee:

Teradyne, Inc., North Reading, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/20 (2006.01); G01R 31/28 (2006.01); G01R 31/312 (2006.01); G01R 31/304 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2815 (2013.01); G01R 31/312 (2013.01); G01R 31/304 (2013.01); G01R 31/318577 (2013.01); Y10T 29/49124 (2015.01);
Abstract

A test system and method for identifying open and shorted connections on a printed circuit board (PCB). An integrated circuit (IC) unit on the PCB is configured to generate a test signal on an output pin connected to a test pin on a second device, connector, or socket on the PCB. For a connection, the test signal is capacitively coupled to a detector plate proximal the second device. Based on the signal coupled to the detector, time domain analysis is performed on the coupled signal to determine if the test pin has a good connection to the PCB or if the pin is open or shorted. Analysis may include cross-correlating the coupled signal with a learned signal obtained from a known 'good' PCB. The test pin may pass the test if the cross-correlation is within a specified threshold window. If the test fails, additional tests may be performed to troubleshoot the cause of the testing failure.


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