The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2017
Filed:
Mar. 26, 2015
Cypress Semiconductor Corporation, San Jose, CA (US);
Eashwar Thiagarajan, Bellevue, WA (US);
Harold M. Kutz, Edmonds, WA (US);
Hans Klein, Pleasanton, CA (US);
Jaskarn Singh Johal, Mukilteo, WA (US);
Jean-Paul Vanitegem, San Jose, CA (US);
Kendall V. Castor-Perry, Seattle, WA (US);
Mark E. Hastings, Mukilteo, WA (US);
Amsby D. Richardson, Jr., Lynnwood, WA (US);
Anasuya Pai Maroor, Woodinville, WA (US);
Ata Khan, Saratoga, CA (US);
Dennis R. Seguine, Temecula, CA (US);
Bruce E. Byrkett, Preston, WA (US);
Carl Ferdinand Liepold, San Jose, CA (US);
Hans Van Antwerpen, Mountain View, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.