The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Jul. 21, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Jeremy A. Wahl, Delmar, NY (US);

Ryan W. Sporer, Mechanicville, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 21/84 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 21/845 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/41791 (2013.01);
Abstract

One disclosed method includes forming a fin in a substrate by etching a plurality of fin-formation trenches, forming a layer of insulating material in the trenches, performing a densification anneal process on the layer of insulating material and, after performing the densification anneal process, performing at least one ion implantation process to form a counter-doped well region in the fin. The method also includes forming an undoped semiconductor material on an exposed upper surface of the fin, recessing the insulating material so as to expose at least a portion of the undoped semiconductor material and forming a gate structure around the exposed portion of the undoped semiconductor material.


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