The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Apr. 15, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Kuo-Cheng Ching, Hsinchu County, TW;

Gwan Sin Chang, Hsinchu, TW;

Zhiqiang Wu, Hsinchu County, TW;

Chih-Hao Wang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66818 (2013.01); H01L 21/30604 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs). An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin.


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