The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Feb. 18, 2016
Applicant:

United Microelectronics Corporation, Hsinchu, TW;

Inventors:

Yen-Liang Wu, Taipei, TW;

Chung-Fu Chang, Tainan, TW;

Yu-Hsiang Hung, Tainan, TW;

Ssu-I Fu, Kaohsiung, TW;

Wen-Jiun Shen, Douliou, TW;

Man-Ling Lu, Gueishan Township, TW;

Chia-Jong Liu, Gaoshu Township, TW;

Yi-Wei Chen, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 29/0649 (2013.01); H01L 29/1054 (2013.01); H01L 29/6656 (2013.01); H01L 29/785 (2013.01);
Abstract

A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.


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