The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

May. 13, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Donald Y. Chao, Zhubei, TW;

Hou-Yu Chen, Zhubei, TW;

Shyh-Horng Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/02664 (2013.01); H01L 21/324 (2013.01); H01L 21/823814 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A method of fabricating a fin field effect transistor (FinFET) includes forming a first fin and a second fin extending upward from a substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, selectively forming a bulbous epitaxial layer covering a portion of each fin, annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide and depositing a metal layer at least in the cavity. The first fin and the second fin are adjacent. A portion of the first fin and a portion of the second fin extend beyond the top surface of the insulation layer. The bulbous epitaxial layer defines an hourglass shaped cavity between adjacent fins.


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