The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Mar. 25, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Lixin Ge, San Diego, CA (US);

P R Chidambaram, San Diego, CA (US);

Haining Yang, San Diego, CA (US);

John Jianhong Zhu, San Diego, CA (US);

Kern Rim, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 49/02 (2006.01); H01L 29/94 (2006.01); H01L 29/66 (2006.01); H01L 27/07 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 27/0716 (2013.01); H01L 28/24 (2013.01); H01L 29/0653 (2013.01); H01L 29/66181 (2013.01); H01L 29/7851 (2013.01); H01L 29/94 (2013.01);
Abstract

A semiconductor device arranged between a source voltage (Vss) and a power voltage (Vdd) may include a first terminal coupled to the power voltage Vdd. The semiconductor device may also include a decoupling capacitor. The decoupling capacitor may include a semiconductor fin coupled to the first terminal, a dielectric layer on the semiconductor fin, and a gate on the dielectric layer. The semiconductor device may further include a second terminal. The second terminal may include a conductive gate resistor coupled in series with the gate of the decoupling capacitor. The second terminal may be coupled to the source voltage Vss via a first interconnect layer (M1).


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