The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2017
Filed:
Feb. 12, 2015
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Han-Chin Chiu, Kaohsiung, TW;
Cheng-Yuan Tsai, Chu-Pei, TW;
Ming-Wei Tsai, Zhudong Township, TW;
Yao-Wen Chang, Taipei, TW;
Wen-Yuan Hsieh, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a structure and method of forming a low damage passivation layer for III-V HEMT devices. In some embodiments, the structure has a bulk buffer layer disposed over a substrate and a device layer of III-V material disposed over the bulk buffer layer. A source region, a drain region and a gate region are disposed above the device layer. The gate region comprises a gate electrode overlying a gate separation layer. A bulk passivation layer is arranged over the device layer, and an interfacial layer of III-V material is disposed between the bulk passivation layer and the device layer in such a way that the source region, the drain region and the gate region extend through the bulk passivation layer and the interfacial layer, to abut the device layer.