The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2017
Filed:
Mar. 15, 2013
Sankaran M Menon, Austin, TX (US);
Rajendra S Yavatkar, Portland, OR (US);
Eyal Dolev, Holon, IL;
Sridhar Valluru, Austin, TX (US);
Ramana Rachakonda, Austin, TX (US);
Sankaran M Menon, Austin, TX (US);
Rajendra S Yavatkar, Portland, OR (US);
Eyal Dolev, Holon, IL;
Sridhar Valluru, Austin, TX (US);
Ramana Rachakonda, Austin, TX (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data.