The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2017
Filed:
Jul. 24, 2013
Applicant:
Sumco Corporation, Tokyo, JP;
Inventors:
Kazuhiro Narahara, Nagasaki, JP;
Sumihisa Masuda, Saga, JP;
Assignee:
SUMCO CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C30B 25/12 (2006.01); C30B 25/18 (2006.01); C30B 25/20 (2006.01); H01L 21/02 (2006.01); C30B 29/06 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
C30B 25/186 (2013.01); C30B 25/20 (2013.01); C30B 29/06 (2013.01); H01L 21/02021 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/02587 (2013.01); H01L 21/02609 (2013.01); H01L 29/045 (2013.01); H01L 29/0657 (2013.01); H01L 29/16 (2013.01); Y10T 428/24488 (2015.01);
Abstract
Provided is a method of producing an epitaxial silicon wafer which has high flatness at the peripheral portion and an epitaxial silicon wafer obtained by the method. In the method of producing an epitaxial silicon wafer, an epitaxial layer is formed on the top surface of a silicon wafer with a chamfered end having a width of 200 μm or less, which surface has a surface orientation of the (100) plane or the (110) plane.