The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2017
Filed:
Sep. 26, 2013
Intel Corporation, Santa Clara, CA (US);
Amr M. Lotfy, Qattameya, EG;
Mohamed A. Abdelsalam, Giza, EG;
Mamdouh O. Abd El-Mejeed, Alexandria, EG;
Nasser A. Kurd, Portland, OR (US);
Mohamed A. Abdelmoneum, Portland, OR (US);
Mark Elzinga, El Dorado, CA (US);
Young Min Park, Folsom, CA (US);
Jagannadha R. Rapeta, Folsom, CA (US);
Surya Musunuri, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.