The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Jun. 17, 2015
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Jhen-Cyuan Li, New Taipei, TW;

Nan-Yuan Huang, Tainan, TW;

Shui-Yen Lu, Tainan, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7853 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/165 (2013.01);
Abstract

A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same.


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