The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Aug. 12, 2015
Applicant:

Unisantis Electronics Singapore Pte. Ltd., Singapore, SG;

Inventors:

Fujio Masuoka, Tokyo, JP;

Masamichi Asano, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 27/12 (2006.01); H03K 19/20 (2006.01); H03K 19/0948 (2006.01); H01L 21/8238 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42392 (2013.01); H01L 21/823828 (2013.01); H01L 21/823885 (2013.01); H01L 27/1203 (2013.01); H01L 27/1207 (2013.01); H01L 29/78 (2013.01); H01L 29/7827 (2013.01); H03K 19/0948 (2013.01); H03K 19/20 (2013.01); H01L 29/78642 (2013.01);
Abstract

A semiconductor device includes a two-input NOR circuit including four MOS transistors arranged in a line. Each of the MOS transistors is disposed on a planar silicon layer disposed on a substrate. The drain, gate, and source of the MOS transistor are arranged in the vertical direction. The gate surrounds a silicon pillar. The planar silicon layer is constituted by a first activation region of a first conductivity type and a second activation region of a second conductivity type. The first and second activation regions are connected to each other via a silicon layer disposed on a surface of the planar silicon layer, so as to form a NOR circuit having a small area.


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