The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Apr. 28, 2016
Applicant:

Avalanche Technology, Inc., Fremont, CA (US);

Inventors:

Kimihiro Satoh, Fremont, CA (US);

Bing K. Yen, Cupertino, CA (US);

Assignee:

Avalanche Technology, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01); H01L 27/22 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/222 (2013.01); H01L 27/224 (2013.01); H01L 27/2409 (2013.01); H01L 27/2427 (2013.01); H01L 27/2481 (2013.01); H01L 45/06 (2013.01); H01L 45/08 (2013.01); H01L 45/1226 (2013.01); H01L 45/141 (2013.01);
Abstract

The present invention is directed to a memory device including a first layer of memory cells with each cell of the first layer of memory cells including a two-terminal selection element coupled to a memory element in series; a plurality of first local wiring lines connected to one ends of the first layer of memory cells along a first direction with each of the first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and a plurality of second local wiring lines connected to other ends of the first layer of memory cells along a second direction substantially orthogonal to the first direction with each of the second local wiring lines being electrically connected to two second line selection transistors at two ends thereof.


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