The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2017
Filed:
Jan. 06, 2016
Applicants:
Sumitomo Electric Industries, Ltd., Osaka, JP;
Sumitomo Electric Device Innovations, Inc., Yokohama-shi, Kanagawa, JP;
Inventors:
Takeshi Araya, Osaka, JP;
Tsutomu Komatani, Yokohama, JP;
Assignees:
SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka, JP;
SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC., Yokohama-shi, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/338 (2006.01); H01L 21/322 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3228 (2013.01); H01L 21/3221 (2013.01); H01L 21/3245 (2013.01); H01L 29/2003 (2013.01); H01L 29/66462 (2013.01); H01L 29/66522 (2013.01); H01L 29/7787 (2013.01);
Abstract
A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.