The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 2017
Filed:
Apr. 16, 2014
Applicant:
Globalfoundries Singapore Pte. Ltd., Singapore, SG;
Inventors:
Lei Wang, Singapore, SG;
Xuesong Rao, Singapore, SG;
Wei Lu, Singapore, SG;
Alex See, Singapore, SG;
Assignee:
GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/311 (2006.01); H01L 21/461 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31055 (2013.01); H01L 21/31053 (2013.01); H01L 21/76256 (2013.01); H01L 21/02271 (2013.01);
Abstract
Methods of forming a semiconductor device are presented. The method includes providing a wafer with top and bottom wafer surfaces. The wafer includes edge and non-edge regions. A dielectric layer having a desired concave top surface is provided on the top wafer surface. The method includes planarizing the dielectric layer to form a planar top surface of the dielectric layer. The desired concave top surface of the dielectric layer thicknesses compensates for different planarizing rates at the edge and non-edge regions of the wafer.