The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Aug. 26, 2015
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Andy Wangkun Chen, Austin, TX (US);

Hsin-Yu Chen, Austin, TX (US);

Sabarish Ittamveetil, Austin, TX (US);

Yew Keong Chong, Austin, TX (US);

Indranil Basu, Bangalore, IN;

Vikash, Bangalore, IN;

Assignee:

ARM Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 5/02 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 8/12 (2006.01); G11C 7/06 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 5/025 (2013.01); G11C 7/106 (2013.01); G11C 7/1075 (2013.01); G11C 7/1087 (2013.01); G11C 7/222 (2013.01); G11C 8/12 (2013.01); G06F 13/28 (2013.01); G11C 7/062 (2013.01);
Abstract

A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal.


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