The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Dec. 16, 2014
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventor:

Rob E. Cosaro, San Jose, CA (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 13/24 (2006.01); G06F 9/44 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/3237 (2013.01); G06F 13/24 (2013.01); G06F 9/4418 (2013.01); Y02B 60/1228 (2013.01);
Abstract

The present disclosure provides for a method and semiconductor device for low power configuration. In one embodiment, a method includes receiving a packet from a host device, where the packet is received at a USB (Universal Serial Bus) device. The method also includes detecting, by the USB device, that the packet includes an endpoint address of a low power endpoint. The method also includes entering a low power mode state, in response to the detecting, where the USB device includes a USB clock domain that includes an internal reference clock (IRC) and clock recovery logic, and a clock tree block located outside of the USB clock domain. The entering the low power mode state includes disabling the clock tree block, and clocking the USB clock domain using the IRC and clock recovery logic.


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