The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Jan. 12, 2012
Applicants:

Veeraraghavan S. Basker, Schenectady, NY (US);

David V. Horak, Essex Junction, VT (US);

Charles W. Koburger, Iii, Delmar, NY (US);

Shom Ponoth, Clifton Park, NY (US);

Chih-chao Yang, Glenmont, NY (US);

Inventors:

Veeraraghavan S. Basker, Schenectady, NY (US);

David V. Horak, Essex Junction, VT (US);

Charles W. Koburger, III, Delmar, NY (US);

Shom Ponoth, Clifton Park, NY (US);

Chih-Chao Yang, Glenmont, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/76897 (2013.01); H01L 29/66628 (2013.01); H01L 29/78 (2013.01);
Abstract

A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.


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