The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2017
Filed:
Nov. 17, 2010
Chien-chih Ho, Hsinchu, TW;
Chih-ping Chao, Hsinchu, TW;
Hua-chou Tseng, Hsinchu, TW;
Chun-hung Chen, Xinpu Township, TW;
Chia-yi Su, Yonghe, TW;
Alex Kalnitsky, San Francisco, CA (US);
Jye-yen Cheng, Taichung, TW;
Harry-hak-lay Chuang, Hsinchu, TW;
Chien-Chih Ho, Hsinchu, TW;
Chih-Ping Chao, Hsinchu, TW;
Hua-Chou Tseng, Hsinchu, TW;
Chun-Hung Chen, Xinpu Township, TW;
Chia-Yi Su, Yonghe, TW;
Alex Kalnitsky, San Francisco, CA (US);
Jye-Yen Cheng, Taichung, TW;
Harry-Hak-Lay Chuang, Hsinchu, TW;
Abstract
A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.