The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Mar. 03, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

James Walter Blatchford, Richardson, TX (US);

Scott William Jessen, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 27/02 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 21/0274 (2013.01); H01L 21/31144 (2013.01); H01L 21/762 (2013.01); H01L 21/76802 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01); H01L 21/76895 (2013.01); H01L 21/823871 (2013.01); H01L 27/0207 (2013.01); H01L 21/0273 (2013.01);
Abstract

A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.


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