The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Aug. 25, 2016
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Meng-Yi Wu, Hsinchu County, TW;

Wei-Zhe Wong, Hsinchu County, TW;

Hsin-Ming Chen, Hsinchu, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/10 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); G11C 11/24 (2006.01); H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
G11C 5/10 (2013.01); G11C 11/24 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 27/11206 (2013.01);
Abstract

A memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor. The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate, and a gate terminal coupled to an antifuse control line. The second following gate transistor and the second select transistor are disposed symmetrically to the first following gate transistor and the second select transistor with respect to the antifuse transistor.


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