The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2017
Filed:
Mar. 11, 2015
Intel Corporation, Santa Clara, CA (US);
Vasudev Bibikar, Austin, TX (US);
Rajesh Poornachandran, Portland, OR (US);
Ajaya V. Durg, Austin, TX (US);
Arpit Shah, Austin, TX (US);
Anil K. Sabbavarapu, Austin, TX (US);
Nabil F. Kerkiz, Austin, TX (US);
Quang T. Le, Austin, TX (US);
Ryan R. Pinto, Austin, TX (US);
Moorthy Rajesh, Folsom, CA (US);
James A. Bish, Antelope, CA (US);
Ranjani Sridharan, Sunnyvale, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.