The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2017
Filed:
Jul. 24, 2013
Cadence Design Systems, Inc., San Jose, CA (US);
Vikas Kohli, Noida, IN;
Amit Kumar Sharma, Greater Noida, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method and system are provided for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design. A circuit editing tool electronically renders schematic representations of circuit objects responsive to user input. A layout object acquisition unit coupled to the circuit editing tool actuates responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit objects for generating a corresponding layout object. The predetermined layout strategy includes a defining set of placement and interconnection routing schemes for the grouped circuit objects, one relative to the other. A layout object management unit coupled to the layout object acquisition unit and circuit editing tool adaptively reconfigures the layout object in accordance with the layout strategy thereof responsive to an editing operation being imposed on at least one circuit object within the layout object.