The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Mar. 24, 2014
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Adam D. Sherer, Chelmsford, MA (US);

Daniel A. Cohen, Los Gatos, CA (US);

John LeRoy Pierce, Temple, NH (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/504 (2013.01);
Abstract

The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing an electronic design including, at least in part, one or more hardware description languages and one or more software programming languages. Embodiments may further include calculating configuration information without analyzing the electronic design, wherein the configuration information includes one or more memory elements configured to control a mode of operation of the electronic design. Embodiments may also include determining a change in the one or more memory elements and altering a function associated with the electronic design verification based upon, at least in part, the determined change.


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