The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Mar. 25, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bill Nale, Livermore, CA (US);

Raj K. Ramanujan, Federal Way, WA (US);

Muthukumar P. Swaminathan, Folsom, CA (US);

Tessil Thomas, Bangalore, IN;

Taarinya Polepeddi, London, GB;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/16 (2006.01); G06F 12/0868 (2016.01); G06F 11/10 (2006.01); G06F 12/0802 (2016.01); G06F 12/0804 (2016.01); G06F 12/0897 (2016.01); G06F 9/46 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 9/467 (2013.01); G06F 11/1064 (2013.01); G06F 12/0802 (2013.01); G06F 12/0804 (2013.01); G06F 12/0868 (2013.01); G06F 12/0897 (2013.01); G06F 13/1694 (2013.01); G06F 13/4068 (2013.01); G06F 13/42 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/2024 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01);
Abstract

A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.


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