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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9619356 B1

PDFFull Text
Expired
Date of Patent:
Apr. 11, 2017

Filed:

Dec. 09, 2015

Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Harold W. Cain, III, Katonah, NY (US);

David M. Daly, Croton-on-Hudson, NY (US);

Kattamuri Ekanadham, Mohegan Lake, NY (US);

Michael C. Huang, Rochester, NY (US);

Jose E. Moreira, Irvington, NY (US);

Mauricio J. Serrano, Bronx, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Daniel P. Morris, Esq.

Otterstedt, Ellenbogen & Kammer, LLP

Primary Examiner:

Joseph Schell

Int. Cl.
CPC ...
G06F 11/273 (2006.01); G06F 11/16 (2006.01); G06F 11/22 (2006.01); G06F 11/26 (2006.01); G06F 11/263 (2006.01); G06F 11/18 (2006.01);
U.S. Cl.
CPC ...
G06F 11/273 (2013.01); G06F 11/1608 (2013.01); G06F 11/181 (2013.01); G06F 11/2242 (2013.01); G06F 11/26 (2013.01); G06F 11/263 (2013.01); G06F 11/1629 (2013.01); G06F 11/18 (2013.01);
Abstract

A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, periodically synchronizing the transaction on the cores throughout execution of the transaction, comparing results of the transaction on the cores, and determining an error in one or more of the cores.

Find Patent Forward Citations

Cain, III, Harold. (2017). Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor (U.S. Patent No. 9619356). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9619356

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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