The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2017
Filed:
Feb. 01, 2016
Qualcomm Incorporated, San Diego, CA (US);
Wilson Chen, San Diego, CA (US);
Chiew-Guan Tan, San Diego, CA (US);
Reza Jalilizeinali, Carlsbad, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (V) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while Vcontinues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when Vbegins transitioning from high to low logic voltages, and transitions back to the low bias voltage while Vcontinues to transition towards the low logic voltage.