The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Aug. 06, 2012
Applicants:

Haizhou Yin, Poughkeepsie, NY (US);

Keke Zhang, Shandong, CN;

Inventors:

Haizhou Yin, Poughkeepsie, NY (US);

Keke Zhang, Shandong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66492 (2013.01); H01L 21/76897 (2013.01); H01L 29/6659 (2013.01); H01L 29/66583 (2013.01); H01L 21/28518 (2013.01);
Abstract

The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover source and drain regions and expose a gate region; forming an interlayer dielectric layer on the substrate to cover the contact sacrificial pattern and expose the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern to form the source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of a contact sacrificial layer process, the method of manufacturing a semiconductor device according to the present invention effectively reduces the distance between the gate spacer and the contact region and increases the area of the contact region, thus effectively reducing the parasitic resistance of the device.


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