The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Aug. 31, 2015
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Shyue Seng Tan, Singapore, SG;

Ying Keung Leung, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/792 (2006.01); H01L 21/762 (2006.01); H01L 21/31 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 27/11521 (2017.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 29/0619 (2013.01); H01L 21/31 (2013.01); H01L 21/762 (2013.01); H01L 27/11521 (2013.01); H01L 27/11568 (2013.01); H01L 29/0653 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/788 (2013.01); H01L 29/792 (2013.01);
Abstract

Devices and methods for forming a device are disclosed. The device includes a substrate with a device region having a length and a width direction. An isolation region surrounds the device region of which an isolation edge abuts the device region. A transistor is disposed in the device region. The transistor includes a gate disposed between first and second source/drain (S/D) regions. A silicide block is disposed on the transistor. The silicide block covers at least the isolation edge adjacent to the gate. The silicide block prevents formation of a silicide contact at least at the isolation edge adjacent to the gate.


Find Patent Forward Citations

Loading…