The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2017
Filed:
Mar. 27, 2015
Intel Corporation, Santa Clara, CA (US);
Davide Mantegazza, Palo Alto, CA (US);
Prashant S. Damle, Santa Clara, CA (US);
Kiran Pangal, Fremont, CA (US);
Hanmant P. Belgal, El Dorado Hills, CA (US);
Abhinav Pandey, Boise, ID (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.