The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Jul. 17, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Subbarao Palacharla, San Diego, CA (US);

Moinul Khan, San Diego, CA (US);

Alain Artieri, San Diego, CA (US);

Kedar Bhole, San Diego, CA (US);

Vinod Chamarty, San Diego, CA (US);

Pankaj Chaurasia, Cupertino, CA (US);

Raghu Sankuratri, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0893 (2016.01); G06F 12/084 (2016.01); G06F 12/12 (2016.01); G06F 12/10 (2016.01); G06F 12/0895 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0893 (2013.01); G06F 12/084 (2013.01); G06F 12/0895 (2013.01); G06F 12/10 (2013.01); G06F 12/12 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/152 (2013.01); G06F 2212/601 (2013.01); G06F 2212/6046 (2013.01); G06F 2212/69 (2013.01); Y02B 60/1225 (2013.01);
Abstract

Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.


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