The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2017
Filed:
Nov. 08, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sathyanarayanan Gopal, Fremont, CA (US);
Sanjib Basu, Bangalore, IN;
Pravas Pradhan, Bangalore, IN;
Prakash K. Radhakrishnan, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3265 (2013.01); G06F 1/26 (2013.01); G06F 1/32 (2013.01); G06F 1/3287 (2013.01); Y02B 60/1242 (2013.01); Y02B 60/1282 (2013.01);
Abstract
By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.