The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Dec. 17, 2012
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Khanh Tran, Milpitas, CA (US);

Joseph P. Ellul, San Jose, CA (US);

Edward M. Godshalk, Newberg, OR (US);

Kiyoko Ikeuchi, Mountain View, CA (US);

Anuranjan Srivastava, Dublin, CA (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/92 (2006.01); H01L 29/66 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/92 (2013.01); H01L 28/91 (2013.01); H01L 29/66083 (2013.01);
Abstract

Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate. The substrate includes multiple capacitor regions, such as a first capacitor region and a second capacitor region that are adjacent to one another. Each capacitor region includes trenches that are formed within the substrate. A metal-insulator-metal capacitor is formed within the trenches and at least partially over the substrate. The trenches disposed within the first capacitor region are at least substantially perpendicular to the trenches disposed within the second capacitor region.


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