The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 2017

Filed:

Jun. 27, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Peter Baars, Dresden, DE;

Hans-Peter Moll, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 27/12 (2006.01); H01L 21/308 (2006.01); H01L 21/321 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 27/06 (2006.01); H01L 49/02 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/308 (2013.01); H01L 21/3212 (2013.01); H01L 21/76224 (2013.01); H01L 21/84 (2013.01); H01L 27/0629 (2013.01); H01L 28/20 (2013.01); H01L 28/40 (2013.01); H01L 29/0847 (2013.01); H01L 29/41783 (2013.01); H01L 29/495 (2013.01); H01L 29/66545 (2013.01); H01L 29/7838 (2013.01);
Abstract

An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.


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