The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2017
Filed:
Nov. 07, 2013
Synopsys, Inc., Mountain View, CA (US);
Prashant Dubey, Uttar Pradesh, IN;
Shivangi Mittal, Delhi, IN;
Raushan Kumar Jha, Uttar Pradesh, IN;
Synopsys, Inc., Mountain View, CA (US);
Abstract
A data storage element comprises a master stage (MS) with a first and a second latch (LI, L), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT) based on an input signal (DATA) in relation to a first threshold level (TP). The second latch generates (L) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT) based on the input signal (DATA) in relation to a second threshold level (TP). The second threshold level (TP) is distinct from the first threshold level (TP). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUT, DOUT) have the same logical state, and with a second logical state they have different logical states. The slave stage (SLS) sets an output value (Q) of the data storage element to a common logical state of the first and the second logical signal (DOUT, DOUT) when the error signal (ER) has the first logical state, and keeps the output value (Q) unchanged otherwise.