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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9601519 B1

PDFFull Text
Date of Patent:
Mar. 21, 2017

Filed:

May. 16, 2016

Thin film transistor and display panel including the same

Applicant:

Innolux Corporation, Miao-Li County, TW;

Inventors:

Hsin-Hung Lin, Miao-Li County, TW;

Jung-Fang Chang, Miao-Li County, TW;

Ker-Yih Kao, Miao-Li County, TW;

Assignee:

INNOLUX CORPORATION, Miao-Li County, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Laura Menz

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01); H01L 21/441 (2006.01); H01L 21/47 (2006.01); H01L 21/471 (2006.01); H01L 21/4757 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); H01L 21/441 (2013.01); H01L 21/47 (2013.01); H01L 21/471 (2013.01); H01L 21/47573 (2013.01); H01L 23/3171 (2013.01); H01L 23/481 (2013.01); H01L 27/1259 (2013.01); H01L 29/41733 (2013.01); H01L 29/41775 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66742 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78606 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A thin film transistor is provided, which includes a gate electrode on a substrate; a channel layer overlapping the gate electrode; a dielectric layer between the gate electrode and the channel layer; a source electrode and a drain electrode electrically connecting to the channel layer; a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer, wherein the channel layer includes two contact portions being in contact with the source electrode and the drain electrode, respectively, and a non-contact portion located between the two contact portions, and wherein one of the two contact portions has a first thickness in a first direction perpendicular to a surface of the substrate, and the non-contact portion has a second thickness less than the first thickness in the first direction.

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