The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

May. 16, 2016
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Mu-Ying Tsao, Changhua County, TW;

Wei-Ren Chen, Pingtung County, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/167 (2006.01); H01L 29/207 (2006.01); H01L 29/227 (2006.01); H01L 31/0288 (2006.01); H01L 27/115 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 23/528 (2006.01); G11C 16/04 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 27/112 (2006.01); H01L 23/525 (2006.01); H01L 29/93 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); G11C 16/0425 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 23/528 (2013.01); H01L 27/11206 (2013.01); H01L 29/0649 (2013.01); H01L 29/42328 (2013.01); H01L 29/42368 (2013.01); H01L 29/4916 (2013.01); H01L 29/512 (2013.01); H01L 29/7817 (2013.01); H01L 29/7835 (2013.01); H01L 23/5252 (2013.01); H01L 29/93 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An NVM array includes a plurality of NVM cells, a plurality of word lines extending along a first direction, a plurality of bit lines extending along a second direction, and a plurality of source lines. Each of the NVM cells includes a PMOS select transistor and a PMOS floating gate transistor serially connected to the PMOS select transistor. Each word line is electrically connected to the select gate of the PMOS select transistor. Each bit line is electrically connected to a doping region of the PMOS floating gate transistor of each of the plurality of NVM cells. Each source line is electrically connected to a doping region of the PMOS select transistor.


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