The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2017
Filed:
Feb. 11, 2016
Applicant:
Intel Deutschland Gmbh, Neubiberg, DE;
Inventors:
Markus Brunnbauer, Lappersdorf, DE;
Thorsten Meyer, Regensburg, DE;
Stephan Bradl, Regensburg, DE;
Ralf Plieninger, Poing, DE;
Jens Pohl, Bernhardswald, DE;
Klaus Pressel, Regensburg, DE;
Recai Sezi, Roettenbach, DE;
Assignee:
Intel Deutschland GmbH, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/301 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/552 (2006.01); H01L 23/60 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/48 (2013.01); H01L 23/5389 (2013.01); H01L 23/552 (2013.01); H01L 23/60 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/20 (2013.01); H01L 2224/97 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01015 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1617 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/3025 (2013.01);
Abstract
A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.