The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9601360 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 21, 2017

Filed:

Mar. 16, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Jyun-Chao Chen, Hsinchu, TW;

Ming-Jung Chen, Hsinchu, TW;

Shao-Yen Ku, Jhubei, TW;

Tsai-Pao Su, Donggang Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/677 (2006.01); H01L 21/673 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67294 (2013.01); H01L 21/67276 (2013.01); H01L 21/67745 (2013.01); H01L 21/673 (2013.01);
Abstract

A wafer transport method is provided. The wafer transport method includes loading an initial carrier containing a first wafer and a second wafer on a first semiconductor apparatus, and processing the first wafer by the first semiconductor apparatus, and loading the first wafer into a first carrier disposed on the first semiconductor apparatus. The wafer transport method also includes processing the second wafer by the first semiconductor apparatus, and loading the second wafer into a second carrier disposed on the first semiconductor apparatus. The wafer transport method further includes processing the first wafer by a second semiconductor apparatus, and loading the first wafer into an integration carrier disposed on the second semiconductor apparatus. The wafer transport method further includes processing the second wafer by the second semiconductor apparatus, and loading the second wafer into the integration carrier disposed on the second semiconductor apparatus.


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