The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2017
Filed:
Aug. 27, 2014
Applicants:
Douglas M. Reber, Austin, TX (US);
Sergio A. Ajuria, Austin, TX (US);
Phuc M. Nguyen, Austin, TX (US);
Inventors:
Douglas M. Reber, Austin, TX (US);
Sergio A. Ajuria, Austin, TX (US);
Phuc M. Nguyen, Austin, TX (US);
Assignee:
NXP USA, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4846 (2013.01); H01L 23/522 (2013.01); H01L 23/585 (2013.01); H01L 24/02 (2013.01); H01L 24/92 (2013.01); H01L 24/94 (2013.01); H01L 22/34 (2013.01); H01L 23/562 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/81 (2013.01); H01L 24/85 (2013.01); H01L 2224/0237 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/039 (2013.01); H01L 2224/0392 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05023 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/1146 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/85048 (2013.01); H01L 2224/8581 (2013.01); H01L 2224/85205 (2013.01); H01L 2224/85207 (2013.01); H01L 2224/92 (2013.01); H01L 2224/9212 (2013.01); H01L 2224/94 (2013.01); H01L 2924/00014 (2013.01);
Abstract
An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.