The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2017
Filed:
Sep. 30, 2011
Raj K. Ramanujan, Federal Way, WA (US);
Rajat Agarwal, Beaverton, OR (US);
Kai Cheng, Portland, OR (US);
Taarinya Polepeddi, London, GB;
Camille C. Raad, Folsom, CA (US);
David J. Zimmerman, El Dorado Hills, CA (US);
Muthukumar P. Swaminathan, Folsom, CA (US);
Dimitrios Ziakas, Hillsboro, OR (US);
Mohan J. Kumar, Aloha, OR (US);
Bassam N. Coury, Dupont, WA (US);
Glenn J. Hinton, Portland, OR (US);
Raj K. Ramanujan, Federal Way, WA (US);
Rajat Agarwal, Beaverton, OR (US);
Kai Cheng, Portland, OR (US);
Taarinya Polepeddi, London, GB;
Camille C. Raad, Folsom, CA (US);
David J. Zimmerman, El Dorado Hills, CA (US);
Muthukumar P. Swaminathan, Folsom, CA (US);
Dimitrios Ziakas, Hillsboro, OR (US);
Mohan J. Kumar, Aloha, OR (US);
Bassam N. Coury, Dupont, WA (US);
Glenn J. Hinton, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as 'far memory.' Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as 'near memory.'