The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2017
Filed:
Dec. 24, 2013
Joydeep Ray, Folsom, CA (US);
Varghese George, Folsom, CA (US);
Inder M. Sodhi, Folsom, CA (US);
Jeffrey R. Wilcox, El Dorado Hills, CA (US);
Joydeep Ray, Folsom, CA (US);
Varghese George, Folsom, CA (US);
Inder M. Sodhi, Folsom, CA (US);
Jeffrey R. Wilcox, El Dorado Hills, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Technologies for one-level memory (1LM) and two-level memory (2LM) configurations in a common platform are described. A processor includes a first memory interface coupled to a first memory device that is located off-package of the processor and a second memory interface coupled to a second memory device that is located off-package of the processor. The processor also includes a multi-level memory controller (MLMC) coupled to the first memory interface and the second memory interface. The MLMC includes a first configuration and a second configuration. The first memory device is a random access memory (RAM) of a one-level memory (1LM) architecture in the first configuration. The first memory device is a first-level RAM of a two-level memory (2LM) architecture in the second configuration and the second memory device is a second-level non-volatile memory (NVM) of the 2LM architecture in the second configuration.