The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9595642 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 14, 2017

Filed:

Jun. 29, 2015
Applicant:

Point Engineering Co., Ltd., Asan-si, KR;

Inventors:

Ki Myung Nam, Cheonan-si, KR;

Young Woon Jeon, Ansan-si, KR;

Kyoung Ja Yun, Cheonan-si, KR;

Assignee:

Point Engineering Co., Ltd., Asan-si, Chungcheongnam-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/36 (2010.01); H01L 33/50 (2010.01); H01L 33/48 (2010.01); H01L 33/52 (2010.01); H01L 33/58 (2010.01); H01L 33/54 (2010.01); H01L 33/62 (2010.01);
U.S. Cl.
CPC ...
H01L 33/483 (2013.01); H01L 33/54 (2013.01); H01L 33/58 (2013.01); H01L 33/62 (2013.01);
Abstract

A chip substrate includes laminated conductive portions, and laminated insulation portions that electrically isolate the conductive portions, with a cavity in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate. The substrate includes an insulation layer on the upper surface, excluding a region of the cavity, and a continuous plating layer along a periphery of the chip substrate on the insulation layer. A portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer. A chip package includes a chip substrate, with an optical element sealed in the cavity by a sealing member or lens.


Find Patent Forward Citations

Nam, Ki. (2017). Chip substrate comprising a plated layer and chip package using the same (U.S. Patent No. 9595642). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9595642

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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