The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Feb. 18, 2016
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Hiroyuki Ogawa, Yokkaichi, JP;

Makoto Yoshida, Yokkaichi, JP;

Kazutaka Yoshizawa, Yokkaichi, JP;

Takuya Ariki, Yokkaichi, JP;

Toru Miwa, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01);
Abstract

Word line switches in a word line decoder circuitry for a three-dimensional memory device can be formed as vertical field effect transistors overlying contact via structures to the electrically conductive layers for word lines. Via cavities in a dielectric material portion overlying stepped surfaces of the electrically conductive layers can be filled with a conductive material and recessed to form contact via structures. After forming lower active regions in the recesses, gate electrodes can be formed and patterned to form openings in areas overlying the contact via structures. Gate dielectrics can be formed on the sidewalls of the openings, and transistor channels can be formed inside the openings of the gate electrodes. Upper active regions can be formed over the transistor channels.


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