The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Mar. 24, 2014
Applicant:

Seagate Technology Llc, Cupertino, CA (US);

Inventors:

Zhengang Chen, San Jose, CA (US);

David Patmore, San Jose, CA (US);

Yingji Ju, Shanghai, CN;

Erich F. Haratsch, San Jose, CA (US);

Assignee:

Seagate Technology LLC, Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/44 (2006.01); G11C 29/42 (2006.01); H04L 1/00 (2006.01); G06F 11/00 (2006.01); G11C 7/10 (2006.01); G11C 16/00 (2006.01);
U.S. Cl.
CPC ...
G11C 29/44 (2013.01); G11C 29/42 (2013.01); G06F 11/00 (2013.01); G11C 7/10 (2013.01); G11C 16/00 (2013.01); H04L 1/00 (2013.01);
Abstract

An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to blocks of the memory that are not marked as bad on a block list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to perform a plurality of scans on the memory. The scans are configured to (a) identify the bad blocks, and (b) mark the bad blocks as bad on the block list.


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