Adaptive selective bit line pre-charge for current savings and fast programming

Abstract

Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times during a programming operation. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit line pre-charging may occur for lower data states but not for higher data states. Similarly, during the higher program loop numbers, bit line pre-charging may occur for higher data states but not for lower data states. In another approach, which may or may not incorporate knowledge of the different phases of a programming operation, the setting of the bit line pre-charge can be updated at least once after it is initially set in the verify portion.